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Company Qualcomm
Website www.qualcomm.co.in
Eligibility Master's Degree
Experience 2 - 5 yrs
Location Bangalore
Job Role Engineer - DFT
JOB SUMMARY:
Company Profile:
Qualcomm Incorporated is a world leader in 3G, 4G and next-generation wireless technologies. For nearly 30 years, Qualcomm’s ideas and inventions have fueled major technology trends, transforming the way people work, live and play. Over the years, Qualcomm Incorporated and its subsidiaries have successfully anticipated big industry challenges and made early stage technology investments.
Job Description :
Responsibility :
1. Analyze, propose best compression that can be achieved
2. Own and deliver scan insertion, validate equivalence check
3. Debug/resolve any DRC issues, identify solution and work with front-end team to ensure DFT DRC’s are fixed.
4. Analyzing and meeting ATPG coverage goals >99.5% for static and >90% for TDF
5. Own and deliver MBIST insertion, validate Memory test
6. Own RTL and Gate level simulations for Scan and Memory test vectors
7. Owns STA constraints and work with STA team to resolve timing violations
8. Owns IDDQ constraints generation and validation
9. Support silicon bring-up and debug
1. Master's, Electrical Engineering
1. Minimum of 2-5 year experience in the area of ASIC/DFT
2. In depth knowledge of DFT concepts
3. In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
4. In depth knowledge and hands on experience in MBIST insertion and Memory test validation
5. Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
6. Expertise in scripting languages such as perl, shell, etc.
7. Experience in RTL and Gate level simulations of scan and MBIST test vectors
8. Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)
9. Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
10. Ability to work in an international team, dynamic environment
11. Ability to learn and adapt to new tools and methodologies.
12. Ability to do multi-tasking & work on several high priority designs in parallel.
13. Excellent problem solving skills
14. Excellent communication and team work skills and good English is required
Company Qualcomm
Website www.qualcomm.co.in
Eligibility Master's Degree
Experience 2 - 5 yrs
Location Bangalore
Job Role Engineer - DFT
JOB SUMMARY:
Company Profile:
Qualcomm Incorporated is a world leader in 3G, 4G and next-generation wireless technologies. For nearly 30 years, Qualcomm’s ideas and inventions have fueled major technology trends, transforming the way people work, live and play. Over the years, Qualcomm Incorporated and its subsidiaries have successfully anticipated big industry challenges and made early stage technology investments.
Job Description :
Responsibility :
1. Analyze, propose best compression that can be achieved
2. Own and deliver scan insertion, validate equivalence check
3. Debug/resolve any DRC issues, identify solution and work with front-end team to ensure DFT DRC’s are fixed.
4. Analyzing and meeting ATPG coverage goals >99.5% for static and >90% for TDF
5. Own and deliver MBIST insertion, validate Memory test
6. Own RTL and Gate level simulations for Scan and Memory test vectors
7. Owns STA constraints and work with STA team to resolve timing violations
8. Owns IDDQ constraints generation and validation
9. Support silicon bring-up and debug
Candidate Profile:
1. Master's, Electrical Engineering
Skills/Experience:
1. Minimum of 2-5 year experience in the area of ASIC/DFT
2. In depth knowledge of DFT concepts
3. In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
4. In depth knowledge and hands on experience in MBIST insertion and Memory test validation
5. Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
6. Expertise in scripting languages such as perl, shell, etc.
7. Experience in RTL and Gate level simulations of scan and MBIST test vectors
8. Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)
9. Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
10. Ability to work in an international team, dynamic environment
11. Ability to learn and adapt to new tools and methodologies.
12. Ability to do multi-tasking & work on several high priority designs in parallel.
13. Excellent problem solving skills
14. Excellent communication and team work skills and good English is required
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